// c8051f020.h
// Device specific definitions for the cygnal C8051F020 microprocessor
// (C) Ricky White 2004
///////////////////////////////////////////////////////////////////////////////

#ifndef C8051F020
#define C8051F020

/*  BYTE Registers  */
sfr at 0x80 P0;		/* PORT 0                                        */
sfr at 0x81 SP;		/* STACK POINTER                                 */
sfr at 0x82 DPL;	/* DATA POINTER - LOW BYTE                       */
sfr at 0x83 DPH;	/* DATA POINTER - HIGH BYTE                      */
sfr at 0x84 P4;		/* SFR PAGE SELECT                               */
sfr at 0x85 P5;		/* SFR STACK NEXT PAGE                           */
sfr at 0x86 P6;		/* SFR STACK LAST PAGE                           */
sfr at 0x87 PCON;	/* POWER CONTROL                                 */
sfr at 0x88 TCON;	/* Timer Control */
sfr at 0x89 TMOD;
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;
sfr at 0x8E CKCON;
sfr at 0x8F PSCTL;
sfr at 0x90 P1;
sfr at 0x91 TMR3CN;
sfr at 0x92 TMR3RLL;
sfr at 0x93 TMR3RLH;
sfr at 0x94 TMR3L;
sfr at 0x95 TMR3H;
sfr at 0x96 P7;
//sfr at 0x97 	/* not allocated */
sfr at 0x98 SCON0;
volatile sfr at 0x99 SBUF0;
sfr at 0x9A SPI0CFG;
sfr at 0x9B SPICDAT;
sfr at 0x9C ADC1;
sfr at 0x9D SPI0CKR;
sfr at 0x9E CPT0CN;
sfr at 0x9F CPT1CN;
sfr at 0xA0 P2;
sfr at 0xA1 EMIOTC;
//sfr at 0xA2 /* unused */
sfr at 0xA3 EMI0CF;
sfr at 0xA4 P0MDOUT;
sfr at 0xA5 P1MDOUT;
sfr at 0xA6 P2MDOUT;
sfr at 0xA7 P3MDOUT;
sfr at 0xA8 IE;
sfr at 0xA9 SADDR0;
sfr at 0xAA ADC1CN;
sfr at 0xAB ADC1CF;
sfr at 0xAC AMX1SL;
sfr at 0xAD P3IF;
sfr at 0xAE SADEN1;
sfr at 0xAF EMIOCN;
//sfr at 0xB0 ; /* unused */
sfr at 0xB1 OSCXCN;
sfr at 0xB2 OSCICN;
// sfr at 0xB3 /* unused */ 
// sfr at 0xB4 /* unused */
sfr at 0xB5 P74OUT;
sfr at 0xB6 FLSCL;
sfr at 0xB7 FLACL;
sfr at 0xB8 IP;
sfr at 0xB9 SADEN0;
sfr at 0xBA AMX0CF;
sfr at 0xBB AMX0SL;
sfr at 0xBC ADC0CF;
sfr at 0xBD P1MDIN;
sfr at 0xBE ADC0L;
sfr at 0xBF ADC0H;
sfr at 0xC0 SMB0CN;
sfr at 0xC1 SMB0STA;
sfr at 0xC2 SMB0DAT;
sfr at 0xC3 SMB0ADR;
sfr at 0xC4 ADC0GTL;
sfr at 0xC5 ADC0GTH;
sfr at 0xC6 ADC0LTL;
sfr at 0xC7 ADC0LTH; 
sfr at 0xC8 T2CON;
sfr at 0xC9 T4CON;
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
// sfr at 0xCE /* unused */
sfr at 0xCF SMB0CR;
sfr at 0xD0 PSW;
sfr at 0xD1 REF0CN;
sfr at 0xD2 DAC0L;
sfr at 0xD3 DAC0H;
sfr at 0xD4 DAC0CN;
sfr at 0xD5 DAC1L;
sfr at 0xD6 DAC1H;
sfr at 0xD7 DAC1CN;
sfr at 0xD8 PCA0CN;
sfr at 0xD9 PCA0MD;
sfr at 0xDA PCA0CPM0;
sfr at 0xDB PCA0CPM1;
sfr at 0xDC PCA0CPM2;
sfr at 0xDD PCA0CPM3;
sfr at 0xDE PCA0CPM4;
// sfr at 0xDF /* unused */
sfr at 0xE0 ACC;
sfr at 0xE1 XBR0;
sfr at 0xE2 XBR1;
sfr at 0xE3 XBR2;
sfr at 0xE4 RCAP4L;
sfr at 0xE5 RCAP4H;
sfr at 0xE6 EIE1;
sfr at 0xE7 EIE2;
sfr at 0xE8 ADC0CN;
sfr at 0xE9 PCA0L;
sfr at 0xEA PCA0CPL0;
sfr at 0xEB PCA0CPL1; 
sfr at 0xEC PCA0CPL2;
sfr at 0xED PCA0CPL3;
sfr at 0xEE PCA0CPL4;
// sfr at 0xEF /* unused */
sfr at 0xEF RSTSRC;
sfr at 0xF0 B;
sfr at 0xF1 SCON1;
sfr at 0xF2 SBUF1;
sfr at 0xF3 SADDR1;
sfr at 0xF4 TL4;
sfr at 0xF5 TH4;
sfr at 0xF6 EIP1;
sfr at 0xF7 EIP2;
sfr at 0xF8 SPI0CN;
sfr at 0xF9 PCA0H;
sfr at 0xFA PCA0CPH0;
sfr at 0xFB PCA0CPH1;
sfr at 0xFC PCA0CPH2;
sfr at 0xFD PCA0CPH3;
sfr at 0xFE PCA0CPH4;
sfr at 0xFF WDTCN;


/*  BIT Registers  */
/*  P0  0x80 */
sbit at 0x80 P0_0;
sbit at 0x81 P0_1;
sbit at 0x82 P0_2;
sbit at 0x83 P0_3;
sbit at 0x84 P0_4;
sbit at 0x85 P0_5;
sbit at 0x86 P0_6;
sbit at 0x87 P0_7;

/*  TCON  0x88 */
sbit at 0x88 IT0     ;	/* EXT. INTERRUPT 0 TYPE                         */
sbit at 0x89 IE0     ;  /* EXT. INTERRUPT 0 EDGE FLAG                    */
sbit at 0x8A IT1     ;  /* EXT. INTERRUPT 1 TYPE                         */
sbit at 0x8B IE1     ;  /* EXT. INTERRUPT 1 EDGE FLAG                    */
sbit at 0x8C TR0     ;  /* TIMER 0 ON/OFF CONTROL                        */
sbit at 0x8D TF0     ;  /* TIMER 0 OVERFLOW FLAG                         */
sbit at 0x8E TR1     ;  /* TIMER 1 ON/OFF CONTROL                        */
sbit at 0x8F TF1     ;  /* TIMER 1 OVERFLOW FLAG                         */

/*  P1  0x90 */
sbit at 0x90 P1_0;
sbit at 0x91 P1_1;
sbit at 0x92 P1_2;
sbit at 0x93 P1_3;
sbit at 0x94 P1_4;
sbit at 0x95 P1_5;
sbit at 0x96 P1_6;
sbit at 0x97 P1_7;

/*  SCON0  0x98 */
sbit at 0x98 RI0;
sbit at 0x99 TI0;
sbit at 0x9A RB80;
sbit at 0x9B TB80;
sbit at 0x9C REN0;
sbit at 0x9D SM20;
sbit at 0x9D TXCOL0;
sbit at 0x9E SM10;
sbit at 0x9E RXOV0;
sbit at 0x9F SM00;
sbit at 0x9F FE0;

/*  P2  0xA0 */
sbit at 0xA0 P2_0;
sbit at 0xA1 P2_1;
sbit at 0xA2 P2_2;
sbit at 0xA3 P2_3;
sbit at 0xA4 P2_4;
sbit at 0xA5 P2_5;
sbit at 0xA6 P2_6;
sbit at 0xA7 P2_7;

/*  IE 0xA7*/
sbit at 0xA8 EX0;
sbit at 0xA9 ET0;
sbit at 0xAA EX1;
sbit at 0xAB ET1;
sbit at 0xAC ES0;
sbit at 0xAD ET2;
sbit at 0xAE IEGF0;
sbit at 0xAF EA;

/*  P3  0xB0 */
sbit at 0xB0 P3_0;
sbit at 0xB1 P3_1;
sbit at 0xB2 P3_2;
sbit at 0xB3 P3_3;
sbit at 0xB4 P3_4;
sbit at 0xB5 P3_5;
sbit at 0xB6 P3_6;
sbit at 0xB7 P3_7;

/*  IP 0xB7  */
sbit at 0xB8 PX0;
sbit at 0xB9 PT0;
sbit at 0xBA PX1;
sbit at 0xBB PT1;
sbit at 0xBC PS0;
sbit at 0xBD PT2;
// sbit at 0xBE ; /* unused */
// sbit at 0xBF ; /* unused */

/* SMB0CN 0xC0 */
sbit at 0xC0 TOE;	/* SMbus timeout enable bit */
sbit at 0xC1 FTE;	/* SMbus free Timer Enable bit */
sbit at 0xC2 AA;	/* SMbus Asert Acknowlege */
sbit at 0xC3 SI;	/* SMbus Serial interrupt flag */
sbit at 0xC4 STO;	/* SMbus Stop Flag */
sbit at 0xC5 STA;	/* SMbus Start Flag */
sbit at 0xC6 ENSMB;	/* SMbus Enable */
sbit at 0xC7 BUSY;	/* SMbus Busy Status Flag */

/* T2CON 0xC8 */
sbit at 0xC8 T2CON_0;	sbit at 0xC8 CP_RL2;
sbit at 0xC9 T2CON_1;	sbit at 0xC9 C_T2;
sbit at 0xCA T2CON_2;	sbit at 0xCA TR2;
sbit at 0xCB T2CON_3;	sbit at 0xCB EXEN2;
sbit at 0xCC T2CON_4;	sbit at 0xCC TCLK0;
sbit at 0xCD T2CON_5;	sbit at 0xCD RCLK0;
sbit at 0xCE T2CON_6;	sbit at 0xCE EXF2;
sbit at 0xCF T2CON_7;	sbit at 0xCF TF2;


/*  PSW 0xD0  */
sbit at 0xD0 P; sbit at 0xD0 PARITY;
sbit at 0xD1 F1;
sbit at 0xD2 OV;
sbit at 0xD3 RS0;
sbit at 0xD4 RS1;
sbit at 0xD5 F0;
sbit at 0xD6 AC;
sbit at 0xD7 CY;

/* PCA0CN 0xD8 */
/* PCA Control Register */
sbit at 0xD8 CCF0;	/* PCA0 Module 0 Capture/Compare Flag */
sbit at 0xD9 CCF1;	/* PCA0 Module 1 Capture/Compare Flag */
sbit at 0xDA CCF2;	/* PCA0 Module 2 Capture/Compare Flag */
sbit at 0xDB CCF3;	/* PCA0 Module 3 Capture/Compare Flag */
sbit at 0xDC CCF4;	/* PCA0 Module 4 Capture/Compare Flag */
// sbit at 0xDD		/* unused, read 0, write don't care */
sbit at 0xDE CR;	/* PCA 0  Counter/Timer Run Control */
sbit at 0xDF CF;	/* PCA 0  Counter/Timer Overflow Flag */

/* ACC 0xE0 */
/* accumulator bit access */
sbit at 0xE0 ACC_0;
sbit at 0xE1 ACC_1;
sbit at 0xE2 ACC_2;
sbit at 0xE3 ACC_3;
sbit at 0xE4 ACC_4;
sbit at 0xE5 ACC_5;
sbit at 0xE6 ACC_6;
sbit at 0xE7 ACC_7;


/* ADC0CN 0xE8 */
sbit at 0xE8 AD0LJST;	/* ADC0 Left Justify Select */
sbit at 0xE9 AD0WINT;	/* ADC0 Window Compare Interrupt Flag */
sbit at 0xEA AD0CM0;	/* ADC0 Start of conversion mode select bit 0 */
sbit at 0xEB AD0CM1;	/* ADC0 Start of conversion mode select bit 1 */
sbit at 0xEC AD0BUSY;	/* ADC0 Busy Bit */
sbit at 0xED AD0INT;	/* ADC0 Conversion Complete Interrupt Flag */
sbit at 0xEE AD0TM;	/* ADC Track Mode Bit */
sbit at 0xEF AD0EN;	/* ADC0 Enable Bit */

/* B 0xF0 */
sbit at 0xF0 B_0;
sbit at 0xF1 B_1;
sbit at 0xF2 B_2;
sbit at 0xF3 B_3;
sbit at 0xF4 B_4;
sbit at 0xF5 B_5;
sbit at 0xF6 B_6;
sbit at 0xF7 B_7;

/* SPI0CN 0xF8 */
/* SPI COntrol */
sbit at 0xF8 SPIEN;	/* SPI0 Enable Bit */
sbit at 0xF9 MSTEN;	/* Master Mode Enable */
sbit at 0xFA SLVSEL;	/* Slave Selected Flag */
sbit at 0xFB TXBSY;	/* Transmit Busy Flag */
sbit at 0xFC RXOVRN;	/* Receive Overrun Flag */
sbit at 0xFD MODF;	/* Mode Fault Flag */
sbit at 0xFE WCOL;	/* Write COllision Flag */
sbit at 0xFF SPIF;	/* SPI0 Interrupt FLag */


/* BIT definitions for bits that are not directly accessible */

/* TMOD Bits */
#define T0M0	0x01
#define T0M1	0x02
#define C_T0	0x04
#define GATE0	0x08
#define T1M1	0x10
#define C_T1	0x20
#define GATE1	0x40

/* CKCON Bits */
#define T0M	0x08	/* Timer 0 clock select */
#define T1M	0x10	/* Timer 1 clock select */
#define T2M	0x20	/* Timer 2 clock select */
#define T4M	0x40	/* Timer 4 clock select */

/* PSCTL Bits */
#define PSWE	0x01	/* Program Store Write Enable */
#define PSEE	0x02	/* Program Store Erase Enable */
#define SFLE	0x04	/* Scratchpad Flash memory access enable */

/* TMR3CN Bits */
#define T3XCLK	0x01	/* Timer 3 external clock select */
#define T3M	0x02	/* Timer 3 clock select */
#define TR3	0x04	/* Timer 3 Run control */
#define TF3	0x80	/* Timer 3 overflow flag */

/* P7 Bits */
#define P7_0	0x01
#define P7_1	0x02
#define P7_2	0x04
#define P7_3	0x08
#define P7_4	0x10
#define P7_5	0x20
#define P7_6	0x40
#define P7_7	0x80

/* SPI0CFG Bits */
#define SPIFRS0	0x01	/* SPI0 Frame Size, bit 0 */
#define SPIFRS1	0x02	/* SPI0 Frame Size, bit 1 */
#define SPIFRS2	0x04	/* SPI0 Frame Size, bit 2 */
#define BC0	0x08	/* SPI0 Bit Count, bit 0 */
#define BC1	0x10	/* SPI0 Bit Count, bit 1 */
#define BC2	0x20	/* SPI0 Bit Count, bit 2 */
#define CKPOL	0x40	/* SPI0 Clock polarity */
#define CKPHA	0x80	/* SPI0 Clock phase */

/* SPI0DAT Bits  data only no bits*/

/* ADCI Bits, data word register, no bits */

/* SPI0CKR Bits */
#define SCR0	0x01	/* SPI0 Clock Rate */
#define SCR1	0x02
#define SCR2	0x04
#define SCR3	0x08
#define SCR4	0x10
#define SCR5	0x20
#define SCR6	0x40
#define SCR7	0x80

/* CPT0CN Bits */
#define CP0HYN0	0x01	/* Comparator 0 negative hysteresis control, bit 0 */
#define CP0HYN1	0x02	/* Comparator 0 negative hysteresis control, bit 1 */
#define CP0HYP0	0x04	/* Comparator 0 positive hysteresis control, bit 0 */
#define CP0HYP1	0x08	/* Comparator 0 positive hysteresis control, bit 1 */
#define CP0FIF	0x10	/* Comparator 0 Falling Edge Interrupt Flag */
#define CP0RIF	0x20	/* Comparator 0 rising Edge Interrupt Flag */
#define CP0OUT	0x40	/* Comparator 0 Output state flag */
#define CP0EN	0x80	/* Comparator 0 Enable bit */

/* CPT1CN Bits */
#define CP1HYN0	0x01	/* Comparator 1 negative hysteresis control, bit 0 */
#define CP1HYN1	0x02	/* Comparator 1 negative hysteresis control, bit 1 */
#define CP1HYP0	0x04	/* Comparator 1 positive hysteresis control, bit 0 */
#define CP1HYP1	0x08	/* Comparator 1 positive hysteresis control, bit 1 */
#define CP1FIF	0x10	/* Comparator 1 Falling Edge Interrupt Flag */
#define CP1RIF	0x20	/* Comparator 1 rising Edge Interrupt Flag */
#define CP1OUT	0x40	/* Comparator 1 Output state flag */
#define CP1EN	0x80	/* Comparator 1 Enable bit */

/* EMI0TC Bits */
#define EAH0	0x01	/* EMIF Address Hold,bit 0 */
#define EAH1	0x02	/* EMIF Address Hold,bit 1 */
#define EWR0	0x04	/* EMIF /WR and /RD Pulse Width Control, bit 0 */
#define EWR1	0x08	/* EMIF /WR and /RD Pulse Width Control, bit 1 */
#define EWR2	0x10	/* EMIF /WR and /RD Pulse Width Control, bit 2 */
#define EWR3	0x20	/* EMIF /WR and /RD Pulse Width Control, bit 3 */
#define EAS0	0x40	/* EMIF Address setup time, bit 0 */
#define EAS1	0x80	/* EMIF Address setup time, bit 1 */

/* EMI0CF Bits */
#define EALE0	0x01	/* ALE pulse width select, bit 0 */
#define EALE1	0x02	/* ALE pulse width select, bit 1 */
#define EMD0	0x04	/* EMIF operating mode select, bit 0 */
#define EMD1	0x08	/* EMIF operating mode select, bit 1 */
#define EMD2	0x10	/* EMIF Multiplex mode select */
#define PRTSEL	0x20	/* EMIF Port Select */

/* FLSCL Bits */
#define FLWE	0x01	/* Flash Read/Write Enable */
#define FRAE	0x40	/* Flash Read Always Enable */
#define FOSE	0x80	/* Flash One shot timer enable */

/* ADC1CN Bits */
#define ADC1CM0	0x02	/* ADC1 Start of conversion mode select, bit 0 */
#define ADC1CM1	0x04	/* ADC1 Start of conversion mode select, bit 1 */
#define ADC1CM2	0x08	/* ADC1 Start of conversion mode select, bit 2 */
#define AD1BUSY	0x10	/* ADC1 Busy bit */
#define AD1INT	0x20	/* ADC1 Conversion complete interrupt flag */
#define AD1TM	0x40	/* ADC1 Track mode bit */
#define AD1EN	0x80	/* ADC1 Enable */

/* ADC1CF Bits */
#define AMP1GN0	0x01	/* ADC1 Internal amplifier Gain, bit 0 */
#define AMP1GN1	0x02	/* ADC1 Internal amplifier Gain, bit 1 */
#define AD1SC0	0x08	/* ADC1 SAR COnversion clock period bit 0 */
#define AD1SC1	0x10	/* ADC1 SAR COnversion clock period bit 1 */
#define AD1SC2	0x20	/* ADC1 SAR COnversion clock period bit 2 */
#define AD1SC3	0x40	/* ADC1 SAR COnversion clock period bit 3 */
#define AD1SC4	0x80	/* ADC1 SAR COnversion clock period bit 4 */

/* SMB0STA Bits */

/* SMB0ADR Bits */
#define GC	0x01	/* General call address enable */
#define SLV0	0x02	/* Slave address, bit 0 */
#define SLV1	0x04	/* Slave address, bit 1 */
#define SLV2	0x08	/* Slave address, bit 2 */
#define SLV3	0x10	/* Slave address, bit 3 */
#define SLV4	0x20	/* Slave address, bit 4 */
#define SLV5	0x40	/* Slave address, bit 5 */
#define SLV6	0x80	/* Slave address, bit 6 */


/* T4CON Bits */
#define CP_RL4	0x01	/* Timer 4 Capter/Reload select */
#define C_T4	0x02	/* Timer 4 Counter/Timer Select */
#define TR4	0x04	/* Timer 4 Run Control */
#define EXEN4	0x08	/* Timer 4 External Enable */
#define TCLK1	0x10	/* Transmit clock flag for UART 1 */
#define RCLK1	0x20	/* Receive clock flag for UART 1 */
#define EXF4	0x40	/* Timer 4 External Flag */
#define TF4	0x80	/* Timer 4 Overflow Flag */


/* SMB0CR */


/* REF0CN Bits */
#define REFBE	0x01	/* Internal referance buffer enable bit */
#define BIASE	0x02	/* ADC/DAC Bias generater enable bit */
#define TEMPE	0x04	/* Temperature sensor enable bit */
#define AD1VRS	0x08	/* ADC1 Voltage referance select */
#define AD0VRS	0x10	/* ADC0 Voltage referance select */

/* DAC0CN  Bits */
#define DAC0DF0	0x01	/* DAC0 Data format bits, bit 0 */
#define DAC0DF1	0x02	/* DAC0 Data format bits, bit 1 */
#define DAC0DF2	0x04	/* DAC0 Data format bits, bit 2 */
#define DAC0MD0	0x08	/* DAC0 Mode bits, bit 0 */
#define DAC0MD1	0x10	/* DAC0 Mode bits, bit 1 */
#define DAC0EN	0x80	/* DAC0 Enable Bit */

/* DAC1CN Bits */
#define DAC1DF0	0x01	/* DAC1 Data format bits, bit 0 */
#define DAC1DF1	0x02	/* DAC1 Data format bits, bit 1 */
#define DAC1DF2	0x04	/* DAC1 Data format bits, bit 2 */
#define DAC0MD0	0x08	/* DAC0 Mode bits, bit 0 */
#define DAC0MD1	0x10	/* DAC0 Mode bits, bit 1 */
#define DAC0EN	0x80	/* DAC0 Enable Bit */

/* PCA0MD Bits */
#define ECF	0x01	/* PCA Counter/Timer Overflow Interrupt Enable */
#define CPS0	0x02	/* PCA0 Counter/Timer Pulse Select, bit 0 */
#define CPS1	0x04	/* PCA0 Counter/Timer Pulse Select, bit 1 */
#define CPS2	0x08	/* PCA0 Counter/Timer Pulse Select, bit 2 */
#define CIDL	0x80	/* PCA0 Counter/Timer Idle control */

/* PCA0CPM0 Bits */
#define EECF0	0x01	/* ECCF0 Capture/Compare Flag Interrupt Enable */
#define PWM0	0x02	/* PWM0 Pulse WIdth Modulation Mode Enable */
#define TOG0	0x04	/* TOG0 Toggle Function Enable */
#define MAT0	0x08	/* MAT0 Match Function Enable */
#define CAPN0	0x10	/* CAPN0 Capture negative function enable */
#define CAPP0	0x20	/* CAPN0 Capture positive function enable */
#define ECOM0	0x40	/* ECOM0 COmparator function enable */
#define PWM160	0x80	/* PWM160 16-bit PWM Enable */

/* PCA0CPM1 Bits */
#define EECF1	0x01	/* ECCF1 Capture/Compare Flag Interrupt Enable */
#define PWM1	0x02	/* PWM1 Pulse WIdth Modulation Mode Enable */
#define TOG1	0x04	/* TOG1 Toggle Function Enable */
#define MAT1	0x08	/* MAT1 Match Function Enable */
#define CAPN1	0x10	/* CAPN1 Capture negative function enable */
#define CAPP1	0x20	/* CAPN1 Capture positive function enable */
#define ECOM1	0x40	/* ECOM1 COmparator function enable */
#define PWM161	0x80	/* PWM161 16-bit PWM Enable */

/* PCA0CPM2 Bits */
#define EECF2	0x01	/* ECCF2 Capture/Compare Flag Interrupt Enable */
#define PWM2	0x02	/* PWM2 Pulse WIdth Modulation Mode Enable */
#define TOG2	0x04	/* TOG2 Toggle Function Enable */
#define MAT2	0x08	/* MAT2 Match Function Enable */
#define CAPN2	0x10	/* CAPN2 Capture negative function enable */
#define CAPP2	0x20	/* CAPN2 Capture positive function enable */
#define ECOM2	0x40	/* ECOM2 COmparator function enable */
#define PWM162	0x80	/* PWM162 16-bit PWM Enable */

/* PCA0CPM3 Bits */
#define EECF3	0x01	/* ECCF3 Capture/Compare Flag Interrupt Enable */
#define PWM3	0x02	/* PWM3 Pulse WIdth Modulation Mode Enable */
#define TOG3	0x04	/* TOG3 Toggle Function Enable */
#define MAT3	0x08	/* MAT3 Match Function Enable */
#define CAPN3	0x10	/* CAPN3 Capture negative function enable */
#define CAPP3	0x20	/* CAPN3 Capture positive function enable */
#define ECOM3	0x40	/* ECOM3 COmparator function enable */
#define PWM163	0x80	/* PWM163 16-bit PWM Enable */

/* PCA0CPM4 Bits */
#define EECF4	0x01	/* ECCF4 Capture/Compare Flag Interrupt Enable */
#define PWM4	0x02	/* PWM4 Pulse WIdth Modulation Mode Enable */
#define TOG4	0x04	/* TOG4 Toggle Function Enable */
#define MAT4	0x08	/* MAT4 Match Function Enable */
#define CAPN4	0x10	/* CAPN4 Capture negative function enable */
#define CAPP4	0x20	/* CAPN4 Capture positive function enable */
#define ECOM4	0x40	/* ECOM4 COmparator function enable */
#define PWM164	0x80	/* PWM164 16-bit PWM Enable */

/* XBR0 bits, PORT IO Crossbar Reg 0 */
#define SMB0EN	0x01	/* SMBus 0 Bus I/O Enable Bit */
#define SPI0EN	0x02	/* SPIBus 0 Bus I/O Enable Bit */
#define UART0EN	0x04	/* UART0 I/O Enable Bit */
#define PCA0ME0	0x08	/* PCA0 Modlue I/O Enable bits, bit 0 */
#define PCA0ME1	0x10	/* PCA0 Modlue I/O Enable bits, bit 1 */
#define PCA0ME2	0x20	/* PCA0 Modlue I/O Enable bits, bit 2 */
#define ECI0E	0x40	/* PCA0 External Counter Input Enable Bit */
#define CP0E	0x80	/* Comparator 0 Output Enable Bit */

/* XBR1 bits, PORT IO Crossbar Reg 1 */
#define CPIE	0x01	/* CP1 Output enable bit */
#define T0E	0x02	/* T0 Input enable bit */
#define INT0E	0x04	/* /INT0 input enable bit */
#define T1E	0x08	/* T1 Input Enable Bit */
#define INT1E	0x10	/* /INT1 input enable bit */
#define T2E	0x20	/* T2 Input Enable Bit */
#define T2EXE	0x40	/* T2EX Input Enable Bit */
#define SYSCKE	0x80	/* /SYSCLK output enable bit */

/* XBR2 bits, PORT IO Crossbar Reg 2 */
#define CNVSTE	0x01	/* External Convert Start Enable bit */
#define EMIFLE	0x02	/* External Memory Interface low port Enable Bit */
#define UART1E	0x04	/* UART1 IO Enable Bit */
#define T4E	0x08	/* T4 Input enable bit */
#define T4EXE	0x10	/* T4EX Input enable bit */
#define XBARE	0x40	/* Crossbar Enable Bit */
#define WEAKPUD	0x80	/* Weak pullup disable bit */

/* IEI1 bits, Extended Interrupt Enable 1 */
#define ESPI0	0x01	/* Enable SPI0 Interrupt */
#define ESMB0	0x02	/* Enable SMBus0 Interrupt */
#define EWADC0	0x04	/* Enable Window Comparison ADC0 Interrupt */
#define EPCA0	0x08	/* Enable PCA0 Interrupt */
#define ECP0F	0x10	/* Enable comparitor0 (CP0) Falling edge Interrupt */
#define ECP0R	0x20	/* Enable comparitor0 (CP0) rising edge Interrupt */
#define ECP1F	0x40	/* Enable comparitor1 (CP1) Falling edge Interrupt */
#define ECP1R	0x80	/* Enable comparitor1 (CP1) Rising edge Interrupt */

/* IEI2 bits, Extended Interrupt Enable 2 */
#define ET3	0x01	/* Enable timer 3 interrupt */
#define EADC0	0x02	/* Enable ADC0 End of conversion interrupt */
#define ET4	0x04	/* Enable timer 3 interrupt */
#define EADC1	0x08	/* Enable ADC1 End of conversion interrupt */
#define EX6	0x10	/* Enable External Interrupt 6 */
#define EX7	0x20	/* Enable External Interrupt 7 */
#define ES1	0x40	/* Enable UART1 Interrupt */
#define EXVLD	0x80	/* Enable External Clock source valid interrupt */

/* RSTSRC Bits */
#define PINRSF	0x01	/* Hardware Pin Reset Flag */
#define PORSF	0x02	/* Power-on Reset force and flag */
#define MCDRSF	0x04	/* Missing clock detector flag */
#define WDTRSF	0x08	/* Watchdog Timer reset flag */
#define SWRSEF	0x10	/* Software Reset Force and flag */
#define C0RSEF	0x20	/* Comparator 0 (CP0) Reset enable and flag */
#define CNVRSEF	0x40	/* COnvert Start Reset source Enable and flag */


/* SCON1 Bits */
#define RI1	0x01	/* UART1 Receive interrupt flag */
#define TI1	0x02	/* UART1 Transmit Interrupt flag */
#define RB81	0x04	/* UART1 9th bit receive */
#define TB81	0x08	/* UART1 Ninth transmit bit */
#define REN1	0x10	/* UART1 Receiver Enable */
#define SM21	0x20	/* UART1 Multiprocessor communication enable */
#define TXCOL1	0x20
#define SM11	0x40	/* UART1 mode bit */
#define RXOV1	0x40
#define SM01	0x80	/* UART1 mode bit */
#define FE1	0x80


/* EIP1 Bits */
#define PSPI0	0x01	/* SPI0 Interrupt priority control */
#define PSMB0	0x02	/* SMBus0 Interrupt priority control */
#define PWADC0	0x04	/* ADC0 WIndow comparator Interrupt priority control */
#define PPCA0	0x08	/* PCA0 Interrupt priority control */
#define PCP0F	0x10	/* Comparator0 (CP0) Falling Interrupt priority control */
#define PCP0R	0x20	/* Comparator0 (CP0) Rising Interrupt priority control */
#define PCP1F	0x40	/* Comparator0 (CP1) Falling Interrupt priority control */
#define PCP1R	0x80	/* Comparator1 (CP1) Rising Interrupt priority control */

/* EIP2 Bits */
#define PT3	0x01	/* Timer 3 Interrupt priority control */
#define PADC0	0x02	/* ADC0 End of Conversion Interrupt priority control */
#define PT4	0x04	/* Timer 4 Interrupt priority control */
#define PADC1	0x08	/* ADC1 End of Conversion Interrupt priority control */
#define PX6	0x10	/* External Interrupt 6 Priority Control */
#define PX7	0x20	/* External Interrupt 7 Priority Control */
#define EP1	0x40	/* UART1 Interrupt Priority Control */
#define PXVLD	0x80	/* External Clock SOurce valid Interrupt Priority Control */


/* PCON bits */
#define IDLE	0x01	/* IDLE mode select */
#define STOP	0x02	/* Stop mode select */
#define SSTAT1	0x08	/* UART1 Enhanced status mode select */
#define SMOD1	0x10	/* UART1 Baud Rate Double Enable */
#define SSTAT0	0x40	/* UART0 Enhanced status mode select */
#define SMOD0	0x80	/* UART0 Baud Rate Double Enable */

#endif